Taya branch

alu/alu_arch.vhd

@@ -46,6 +46,7 @@ begin
     -- fully combinational process for calculating the output.
     comb: process(opcode_valid, operand_A, operand_B, div_valid)
     begin
+
         case opcode is
             when x"1" => -- add
                 alu_out <= std_logic_vector(signed(operand_A) + signed(operand_B));
@@ -98,10 +99,25 @@ begin
                 alu_ready <= '1';
         end case;
 
+
+        -- Synthesis fails because of this
+        -- div_start <= '1' when opcode = x"6"  else '1' when opcode = x"7" else '0';
+        -- div_do_mod <= '1' when opcode = x"7" else '0';
+
         -- The start signals are done independently.
         -- This is so they don't clutter the case statement.
-        div_start <= '1' when (opcode = x"6" or opcode = x"7") else '0';
-        div_do_mod <= '1' when opcode = x"7" else '0';
+        if opcode = x"6"
+        then
+            div_start <= '1';
+            div_do_mod <= '0';
+        elsif opcode = x"7"
+        then
+            div_start <= '1';
+            div_do_mod <= '1';
+        else
+            div_start <= '0';
+            div_do_mod <= '0';
+        end if;
 
     end process comb;
 end alu;