Taya branch

alu/divider.vhd

@@ -34,7 +34,6 @@ signal loop_counter, loop_counter_nxt: integer range -1 to word_length-1;
 
 signal remainder, quotient: std_logic_vector(31 downto 0);
 signal remainder_nxt, quotient_nxt: std_logic_vector(31 downto 0);
-signal output_nxt: std_logic_vector(31 downto 0);
 
 signal triggered, modulo_flag, done_s: std_logic;
 signal triggered_nxt, modulo_flag_nxt, done_s_nxt: std_logic;