moved adder to module to share resources

alu/adder.vhd

+-- library and package declarations
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity adder is
+    generic (
+        word_length : integer := 32
+    );
+    port (
+        clk: in std_logic;
+        in_A : in std_logic_vector(word_length-1 downto 0);
+        in_B : in std_logic_vector(word_length-1 downto 0);
+        do_add: in std_logic;
+        adder_out   : out std_logic_vector(word_length-1 downto 0)
+    );
+end entity adder;
+
+
+architecture rtl of adder is
+signal operand_A   : signed(word_length-1 downto 0);
+signal operand_B   : signed(word_length-1 downto 0);
+signal carry_in: unsigned(0 downto 0);
+
+begin
+    comb: process(do_add, in_A, in_B)
+
+    begin
+        if do_add = '1'
+        then
+            operand_A <= signed(in_A);
+            operand_B <= signed(in_B);
+            carry_in <= to_unsigned(0, 1);
+        else
+            operand_A <= signed(not(in_A));
+            operand_B <= signed(in_B);
+            carry_in <= to_unsigned(1, 1);
+        end if;
+    end process comb;
+
+    adder_out <= std_logic_Vector(unsigned(operand_A + operand_B) + carry_in);
+
+end architecture rtl;